A typical integrated circuit device (IC) includes a core region 100, as illustrated in FIG. 1, and one or more functional elements or packages such as analog support/conversion circuitry 102. These are connected through an I/O interface 104 to pads 106 that allow the IC to be connected externally to other devices. The voltage levels vary for different portions of the IC, thus requiring special consideration to avoid exposing the various portions of the IC to excessive voltage levels. For instance, the core, I/O interface, and external circuitry to which the pads of the IC connect, typically will each support different voltages. Even within a typical CMOS core, voltages vary depending on the process used. For example, a 0.25 μm process supports voltage levels of the order of 2.5 V±10%; a 0.18 μm process supports voltage levels of the order of 1.8 V±10%; a 0.15 μM process supports voltage levels of the order of 1.5 V±10%, and a 0.13 μm process supports voltage levels of the order of 1.2 V±10%. In contrast, the I/O interface needs to support 3.3 V typically. For ease of understanding the input voltage levels to the core have been identified as VDD and VSS while those for the I/O interface are indicated as VDDIO and VSSIO. Furthermore, the pads may be connected to circuitry operating in the 5 V range. For example, where the IC drives a PCI bus, it is important that the IC can withstand the higher voltages of the system that it is supporting. In order to supply the higher voltage, a dual gate process involving the use of thick gate oxides is commonly used in the case of sub-micron CMOS.
The main concern arises under stress mode conditions when the pads are exposed to high voltages (approximately 5.5 V) by the external circuitry. Furthermore, different stress mode conditions may be identified. In particular, it is common to reduce VDD and VDDIO to 0 V when the circuitry of the IC is not in use, thereby conserving energy.
An IC may typically be operated in one of three modes: (a) Normal mode, in which the core is powered up and drives the pads; (b) Tolerant mode, which is a stress mode in which the pads are raised up to 5.5 V, while the core and I/O interface are powered up (VDD and VDDIO are high); (c) Back-drive mode, which is a stress mode in which the pads are raised up to 5.5 V, while the core and I/O interface arc powered down (VDD and VDDIO are low). Thus back-drive refers to the 5.5 V tolerant interface when there are no power supplies asserted. This condition becomes particularly important in the case of sub-micron CMOS, dual gate process technology in which the oxide breakdown and drain-source junction breakdown is about 3.8 V. Back-drive I/Os have to tolerate 5.5 V at the pads with and without power supplies asserted (commonly referred to as 5 V tolerant level due to the 5 V±10% tolerance). However, under stress mode, sub-micron dual gate devices tend to experience problems such as oxide breakdown, drain-source junction breakdown, current flow to VDDIO, and well charging due to the parasitic internal diode structure of CMOS devices.
FIG. 2 shows a simple I/O interface driver circuit comprising a p-channel (PMOS) pull-up transistor 200 and a n-channel (NMOS) pull-down transistor 210 which accommodate different load conditions under normal operation. When PMOS 200 is on and NMOS 210 is off, the load can be charged up to VDDIO. On the other hand, when PMOS 200 is off and NMOS 210 is on, the load can discharge to VSSIO. Thus the driver's output to the pad will, under normal operation, provide voltages ranging from VDDIO to VSSIO. Since VDDIO (3.3 V±10% under normal operation) is applied to both gates of the transistors 200, 210 one transistor will always be off, thereby avoiding shoot-through current through the driver transistors 200, 210.
However, under 5 V tolerant mode and back-drive mode, the pad 212 is raised to 5.5 V. In order to avoid gate oxide breakdown the voltage drop from drain to gate must not exceed 3.8 V. Similarly, to avoid junction breakdown, the voltage drop from drain to source must not exceed 3.8 V. Furthermore, it is necessary to isolate the receiver input circuitry from the pad under these stress modes. Since, during stress mode, the pad cannot be driven by the pre-driver circuit, both transistors 200, 210 have to be turned off. Turning off the PMOS transistor 200 also avoids current flow from the pad 212 to VDDIO. The PMOS transistor is ideally turned off by tying the gate of PMOS 200 high relative to the high voltage. However, when the pad voltage exceeds VDDIO by VTP, the PMOS will not shut off. The NMOS transistor, in turn, is turned off by applying a low voltage such as VSSIO to the gate of NMOS 210 relative to the drain.
Thus, in the circuit of FIG. 2, during 5 V tolerant mode (5.5 V on the pad) when the gate of PMOS 200 is at VDDIO (i.e. about 3.3 V for 5 V tolerant mode) the drain to gate voltage is 2.2 V and is thus less than the oxide breakdown voltage, which is about 3.8 V. However, this does not turn off transistor 200. The forward biased internal parasitic diode (indicated by reference numeral 216) allows current flow of the order of milliamps. This results in heating of the cell and possible latch-up. In back-drive mode, when VDDIO is 0 V, the situation is even worse. The voltage to the source and gate of PMOS 200 is 0 V. This not only turns the transistor 200 on but also provides a voltage drop of 5.5 V across the drain-source junction and gate oxide which can cause irreparable damage.
One proposed prior art solution proposed for 5 V tolerant mode to reduce the junction voltages of the driver pull-up and pull-down transistors is to use cascoded p-channel pull-up transistors and cascoded n-channel pull-down transistors in the driver circuit, as shown in FIG. 3, in order to split the voltage across two pull-up and two pull-down transistors. The operation remains the same as for the simple circuit of FIG. 2, since one of the transistors in each cascoded pair is always kept on in normal mode, and the other transistor in each cascoded pair performs the toggling function to accommodate the load on the pad. Thus transistors 300 and 312 are always on during normal mode. It will be noted that even with NMOS transistor 300 asserted, current is prevented from flowing through the NMOS transistors 300, 302 by grounding the gate of transistor 302 which switches transistor 302 off.
In back-drive mode the gate voltages of the driver output transistors are raised to prevent gate oxide damage. Also, to avoid current flow through PMOS transistor 312, the gate of PMOS 312 is charged to the same voltage as its drain. In order to prevent parasitic diode well charging, during back-drive mode and 5 V tolerant mode, the floating n-wells of the PMOS transistors 310, 312 are charged up to FW3 and FW5, respectively (the same voltage as their respective drains). The well charging is achieved by adding a PMOS transistor 314 acting as a switch. With the gate of transistor 314 held sufficiently low relative to its source, i.e when the pad voltage is greater than VDDIO by at least a diode drop, the switch is closed and the voltage of the well is brought up to the level of the pad (5.5 V in stress mode). Gate oxide breakdown and current through the PMOS 312 is prevented by including the PMOS transistor 316 acting as a switch which brings up the voltage of the gate of transistor 312 when the gate of transistor 316 is low relative to the pad voltage. However, in addition to the forward biased internal parasitic diode 322, there is a forward biased parasitic diode 320 in transistor 310 and a reverse biased parasitic diode 324. The diode 324 causes leakage current of the order of 10 nA to flow through the diode 324 during back-drive mode. This charges the drain of transistor 310 to 5.5 V which causes gate oxide breakdown and junction breakdown problems for transistor 310.
The present invention seeks to address the problems of the prior art and enhance the tolerance of an I/O interface to provide tolerance during 5 V tolerant and back-drive mode.